1. Technical Field
The present invention relates to a semiconductor integrated circuit.
2. Related Art
In circuits performing signal transmission and reception, a process of matching the impedance of the circuits is necessary in order to improve the interface characteristics thereof.
For example, a semiconductor memory such as a DDR3, which is one example of a semiconductor integrated circuit, also performs an impedance calibration operation in order to improve the interface characteristics of circuits, and the impedance calibration operation is defined in the specification thereof.
To this end, the semiconductor memory includes an impedance calibration circuit for performing the impedance calibration operation.
Referring to FIG. 1, there is shown a semiconductor integrated circuit according to the conventional art, that is, a memory chip 1 includes an impedance calibration circuit and a plurality of memory blocks 10. The impedance calibration circuit includes an impedance control signal generation block ZQ (20) and a plurality of input/output blocks DQ (30).
As illustrated in FIG. 1, the impedance control signal generation block 20 and the plurality of input/output blocks 30 are located in the peripheral area of the memory chip 1.
The impedance control signal generation block 20 is disposed at a specific position of the memory chip 1 and the plurality of input/output blocks 30 are arranged in a row.
The impedance control signal generation block 20 calibrates the values of impedance control signals PCODE<0:N> and NCODE<0:N> through a process of comparing an external resistor with a resistor according to the impedance control signals PCODE<0:N> and NCODE<0:N> in response to an impedance calibration command.
When the resistance value of the external resistor substantially coincides with the resistance value of the resistor according to the impedance control signals PCODE<0:N> and NCODE<0:N>, the impedance control signal generation block 20 substantially maintains the values of the impedance control signals PCODE<0:N> and NCODE<0:N>.
The impedance of the plurality of input/output blocks 30 is set to a target value according to the impedance control signals PCODE<0:N> and NCODE<0:N> provided by the impedance control signal generation block 20.
The impedance control signals PCODE<0: N> and NCODE<0:N> are provided to the plurality of input/output blocks 30 through signal lines, that is, global lines.
When the ‘N’ is 5, since the number of the impedance control signals PCODE<0:N> and NCODE<0:N> is 12, 12 global lines are necessary.
The impedance calibration circuit according to the conventional art is located in the peripheral area of the memory chip 1.
In order to reduce the size of a memory chip, it is necessary to reduce the size of a peripheral area. To this end, it is important to reduce the size of a circuit located in the peripheral area, and it is also important to reduce the number of global lines for signal transfer among circuits.
However, according to the conventional art, since global lines for transmitting the impedance control signals PCODE<0:N> and NCODE<0:N> are necessarily provided as illustrated in FIG. 1, it is difficult to reduce the chip size.